1. Field of the Invention
This invention relates to data communications comparators and, in particular, to integrated circuit data communications receivers of the comparator type.
2. Description of Related Art
Integrated circuit receivers enjoy widespread use in data communications. For example, in an Ethernet system, data signals are differential signals transmitted over a twisted pair. The data signals are generally of a sine wave character. The data signals are shaped in a receiver, which typically is a type of comparator.
An example of a comparator for receiving Ethernet signals is shown in FIG. 1. Input signals enter the comparator 10 at nodes 11 and 12. The input signals are amplified and buffered by the network consisting of transistors 51, 52, 55, 56, 61, 62, 63, and resistors 53, 54. The amplified and buffered signals at nodes 15 and 16 are then amplified by inverting amplifiers 81, 83 and 82 84, respectively, to yield the output signals from the comparator 10 at nodes 19 and 20.
One problem encountered with the use of comparators to shape transmitted signals is that an unpredictable bias offset (which is the deviation of bias levels from their ideal values) can arise in the comparator so that the relative transitions between logic levels at the comparator output are distorted. Types of distortion typically encountered include, for example, phase distortion and duty cycle distortion. In phase distortion, the rising and falling edge of the comparator output waveform jitters or appears faster or slower than would be expected. In duty cycle distortion, the duty cycle of the comparator output differs from the duty cycle of the transmitted data signal at the comparator input. The bias offset results from, for instance, fluctuation in circuit parameters due to process and temperature changes and power supply noise.
In the comparator 10 shown in FIG. 1, bias generation circuitry consisting of differential amplifier 70, inverting amplifier 74, transistors 71, 72, 75 and resistor 73 is provided to overcome the problem of bias offset. The bias generation circuitry generates a current through the transistor 75 which, in turn, is mirrored in the transistors 61, 62 and 63. The components in the bias generation circuitry are matched With other components in the comparator 10 so that an appropriate amount of current will flow through the transistors 61, 62, 63 to keep the inverting amplifiers 81 and 82 biased in their high gain region when the inputs at nodes 11 and 12 are equal.
This circuit is inadequate for some applications because mismatch of currents in the transistors 75, 61, 62 and 63, or mismatch of device values between transistors 71, 55, 56 or resistors 73, 53, 54 will prevent the inverting amplifiers 81 and 82 from being properly biased. This circuit is also inadequate because it does not act to minimize the detrimental effects arising from the presence of noise in the power supply.
It is desirable, then, to provide a comparator in which fluctuations in the bias offset and the effects of power supply noise are minimized.